Publications

Jourals

J7. [Nature Scientific Reports ‘2022] Yuqi Liu, Weidong Cao, Weijian Chen, Hua Wang, Lan Yang, Xuan Zhang, “Fully integrated topological electronics”, Scientific Reports volume 12, Article number: 17010 (2022), Equal contribution.

J6. [Nature Nanotechnology ‘2022] Weidong Cao, Changqing Wang, Weijian Chen, Song Hu, Hua Wang, Lan Yang, Xuan Zhang, “Fully integrated parity–time-symmetric electronics”, Nature Nanotechnology 17, 262–268 (2022), [pdf],[pdf_arXiv], [Phys.org], [Mirage News], [True Viral News], [Bioengineer.org], [ScienMag], [Newswise], [Nanowerk].

J5. [TC ‘2021] Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, Li Jiang, “Neural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals”, IEEE Transactions on Computers, Early Access, 2021, [pdf], [WashU News], [ScienceDaily].

J4. [TCAD ‘2021] Weidong Cao, Liu Ke, Ayan Chakrabarti, Xuan Zhang, “Evaluating Neural Network-Inspired Analog-to-Digital Conversion With Low-Precision RRAM”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 5, pp. 808-821, 2021, [pdf].

J3. [TCAD ‘2020] Weidong Cao, Xin He, Ayan Chakrabarti, Xuan Zhang, “NeuADC: Neural Network-Inspired Synthesizable Analog-to-Digital Conversion”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 1, pp. 1841-1854, 2020, [pdf].

J2. [Microelectronics journal ‘2018] Fangxu Lv, Xuqiang Zheng, Feng Zhao, Jianye Wang, Shigang Yue, Ziqiang Wang, Weidong Cao, Yajun He, Chun Zhang, Hanjun Jiang, Zhihua Wang, “A power scalable 2–10 Gb/s PI-based clock data recovery for multilane applications”, Microelectron. J. 82 (2018) 36–45, [pdf].

J1. [Microelectronics ‘2015] Weidong Cao, Chenlong Hou, Jinxing Guo, Yilin Song, Ziqiang Wang, Hanjun Jiang, Zhihua Wang, “Design and implementation of a 20GHz VCO,” Microelectronics, 2015, 5, 577-580.

Conference

c10. [ICCAD ‘2022] Huifeng Zhu, Zhiyuan Yu, Weidong Cao, Ning Zhang, Xuan Zhang, “[PowerTouch: A Security Objective-Guided Automation Framework for Generating Wired Ghost Touch Attacks on Touchscreens]”, 2022 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Accepted.

c9. [ISLPED ‘2022, Best Paper Award] Tianrui Ma, Weidong Cao, Fei Qiao, Ayan Chakrabarti, Xuan Zhang, “HOGEye: Neural Approximation of HOG Feature Extraction in RRAM-Based 3D-Stacked Image Sensors,” 2022 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), [pdf].

c8. [DAC ‘2022, Best Paper Nominee] Weidong Cao, Mouhacine Benosman, Xuan Zhang, Rui Ma, “Domain Knowledge-Infused Deep Learning for Automated Analog/Radio-Frequency Circuit Parameter Optimization,” 2022 IEEE/ACM Design Automation Conference (DAC), [pdf],[pdf_arXiv].

c8. [AAAI-workshop ‘2022] Weidong Cao, Mouhacine Benosman, Xuan Zhang, Rui Ma, “Domain Knowledge-Based Automated Analog Circuit Design with Deep Reinforcement Learning,” Association for the Advancement of Artificial Intelligence 2022, 1st Annual AAAI Workshop on AI to Accelerate Science and Engineering (AI2ASE), [pdf].

C7. [ICCAD ‘2019] Weidong Cao, Liu Ke, Ayan Chakrabarti, Xuan Zhang, “Neural Network-Inspired Analog-to-Digital Conversion to Achieve Super-Resolution with Low-Precision RRAM Devices,” 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), [pdf].

C6. [DATE ‘2019, Best Paper Nominee] Weidong Cao, Xin He, Ayan Chakrabarti, Xuan Zhang, “NeuADC: Neural Network-Inspired RRAM-Based Synthesizable Analog-to-Digital Conversion with Reconfigurable Quantization Support,” 2019 Design, Automation and Test in Europe Conference (DATE), [pdf].

C5. [NEWCAS ‘2016] Naiwen Zhou, Linghan Wu, Ziqiang Wang, Xuqiang Zheng, Weidong Cao, Chun Zhang, Fule Li, Zhihua Wang, “A 28-Gb/s Transmitter with 3-tap FFE and T-coil Enhanced Terminal in 65-nm CMOS Technology,” 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), [pdf].

C4. [NEWCAS ‘2015] Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, Shuai Yuan, Fule Li, Zhihua Wang “A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS,” 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), [pdf].

C3. [EDSSC ‘2015] Weidong Cao, Xuqiang Zheng, Ziqiang Wang, Dongmei Li, Fule Li, Shigang Yue, Zhihua Wang, “A 15Gb/s wireline repeater in 65nm CMOS technology,” 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), [pdf].

C2. [EDSSC ‘2015] Weidong Cao, Ziqiang Wang, Dongmei Li, Fule Li, Zhihua Wang, “A 40Gb/s adaptive equalizer with amplitude approaching technique in 65nm CMOS,” 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), [pdf].

C1. [MWSCAS ‘2015] Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang, “A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS,” 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), [pdf].

Patent

P4. Rui Ma, Mouhacine Benosman, Weidong Cao, “A Method of RF/Analog Circuits Electronic Design Automation based on GCN and Deep Reinforcement Learning,” US63/268,433, pending, 2022.

P3. Weidong Cao, Xuan Zhang, Weijian Chen, Lan Yang, “Fully Integrated Parity-Time Symmetric Electronics,” US17/446,000, pending, 2021.

P2. Weidong Cao, Ziqiang Wang, Shuai Yuan, Ke Huang, Fule Li, “A Low-power 3-tap Decision Feedback Equalizer for the Receiver of High-speed Serial Links,” CN105187342A, 2018.

P1. Weidong Cao, Ziqiang Wang, Xuqiang Zheng, Huang Ke, Fule Li, “A Dynamic Latch with Pull-up PMOS for High-speed Circuit,” CN105187045B, 2017.